hdsken

         This register allows software to control whether or not to perform a handshake with certain peripherals before issuing a reset. These bits are cleared on a cold reset. If these bits are not set, writing to the "hdskreq" register to request a software-triggered handshake will not perform the handshake. 
If the peripheral is being held in reset, then the handshake will be skipped, regardless of whether the handshake enable bit is set or not.

Module Instance	Base Address	Register Address
`i_rst_mgr_rstmgr`	`0xFFD11000`	`0xFFD11010`

Size: 32

Offset: 0x10

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`														`debug_l3noc` `RW 0x0`	`l3noc_dbg` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`l2flushen` `RW 0x0`	`Reserved`				`etrstallen` `RW 0x0`	`fpgahsen` `RW 0x0`	`Reserved`	`mpfe_hmca_drainen` `RW 0x0`

hdsken Fields

Bit	Name	Description	Access	Reset
17	`debug_l3noc`	This field controls whether to perform handshake with L3 NOC before asserting the csdap_rst or/and dbg_rst. If set to 1, the Reset Manager makes a request to the L3 NOC before issuing a reset. If set to 0, the handshake is not performed. This handshake is performed when CS DAP or/and DBG is getting reset but NOC is not getting reset.	`RW`	`0x0`
16	`l3noc_dbg`	This field controls whether to perform handshake with L3 NOC before issuing a reset. If set to 1, the Reset Manager makes a request to the L3 NOC before issuing a reset. If set to 0, the handshake is not performed. This handshake is performed when NOC is getting reset but debug and dap are not getting reset	`RW`	`0x0`
8	`l2flushen`	This field controls whether the L2 cache should be flushed before the L2 cache is reset by a watchdog reset or a software-requested L2 cache reset. If bit to 1, the Reset Manager makes a request to the MPU to perform L2 flush before performing ETR/HMC/FPGA handshakes. If bit to 0, the L2 Flush is not performed. L2 Flush is not performed as a part of warm reset sequence.	`RW`	`0x0`
3	`etrstallen`	Software writes this field 1 to request to the ETR that it stalls its AXI master to the L3 Interconnect. This field controls whether the hardware should perform a handhshake with the ETR before issuing a reset. If set to 1, the Reset Manager handshakes with the ETR. If set to 0, the handshake is not performed.	`RW`	`0x0`
2	`fpgahsen`	This field controls whether to perform handshake with FPGA before issuing a reset. If set to 1, the Reset Manager makes a request to the FPGA before issuing a reset. If set to 0, the handshake is not performed.	`RW`	`0x0`
0	`mpfe_hmca_drainen`	This field controls whether to perform handshake with the SDRAM memory interface before issuing a reset. If set to 1, the Reset Manager makes a request to the SDRAM memory interface before issuing a reset. If set to 0, the handshake is not performed.	`RW`	`0x0`