IC_DMA_CR

         Name: DMA Control Register
Size: 2 bits
Address Offset: 0x88
Read/Write Access: Read/Write
This register is only valid when DW_apb_i2c is configured
with a set of DMA Controller interface signals (IC_HAS_DMA = 1).
When DW_apb_i2c is not configured for DMA operation, this register
does not exist and writing to the register's address has no
effect and reading from this register address will return zero.
The register is used to enable the DMA Controller interface operation.
There is a separate bit for transmit and receive. This can be programmed
regardless of the state of IC_ENABLE.
      
Module Instance Base Address Register Address
sdm_i_i2c_0_DW_apb_i2c_addr_block1 0xFF8D0100 0xFF8D0188
sdm_i_i2c_1_DW_apb_i2c_addr_block1 0xFF8D0200 0xFF8D0288

Size: 32

Offset: 0x88

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IC_DMA_CR_2_31

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_IC_DMA_CR_2_31

RO 0x0

TDMAE

RW 0x0

RDMAE

RW 0x0

IC_DMA_CR Fields

Bit Name Description Access Reset
31:2 RSVD_IC_DMA_CR_2_31
Reserved bits [31:1] - Read Only
RO 0x0
1 TDMAE
Transmit DMA Enable.
//This bit enables/disables the transmit FIFO DMA
channel.
0 = Transmit DMA disabled
1 = Transmit DMA enabled
Reset value: 0x0
Value Description
0x0 transmit FIFO DMA channel disabled
0x1 Transmit FIFO DMA channel enabled
RW 0x0
0 RDMAE
Receive DMA Enable.
This bit enables/disables the receive FIFO DMA
channel.
0 = Receive DMA disabled
1 = Receive DMA enabled
Reset value: 0x0
Value Description
0x0 Receive FIFO DMA channel disabled
0x1 Receive FIFO DMA channel enabled
RW 0x0