gmacgrp_interrupt_status

         <b> Register 14 (Interrupt Register) </b>  

The Interrupt Status register identifies the events in the MAC that can generate interrupt. All interrupt events are generated only when the corresponding optional feature is selected during core configuration and enabled during operation. Therefore, these bits are reserved when the corresponding features are not present in the core.
      
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF800038
i_emac_emac1 0xFF802000 0xFF802038
i_emac_emac2 0xFF804000 0xFF804038

Size: 32

Offset: 0x38

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_12

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_31_12

RO 0x0

gpiis

RO 0x0

lpiis

RO 0x0

tsis

RO 0x0

reserved_8

RO 0x0

mmcrxipis

RO 0x0

mmctxis

RO 0x0

mmcrxis

RO 0x0

mmcis

RO 0x0

pmtis

RO 0x0

pcsancis

RO 0x0

pcslchgis

RO 0x0

rgsmiiis

RO 0x0

gmacgrp_interrupt_status Fields

Bit Name Description Access Reset
31:12 reserved_31_12
Reserved
RO 0x0
11 gpiis
GPI Interrupt Status

When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on GPIS field (Bits [3:0]) of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. This bit is cleared on reading the lane 0 (GPIS) of Register 56 (Genaral Purpose IO Register). When the GPIO feature is not enabled, this bit is reserved.
RO 0x0
10 lpiis
LPI Interrupt Status

When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
9 tsis
Timestamp Interrupt Status

When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true:
 * The system time value equals or exceeds the value specified in the Target Time High and Low registers.
 * There is an overflow in the seconds register.
 * The Auxiliary snapshot trigger is asserted.
This bit is cleared on reading Bit 0 of the Register 458 (Timestamp Status Register). 

If default Timestamping is enabled, when set, this bit indicates that the system time value is equal to or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this bit. In all other modes, this bit is reserved.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
8 reserved_8
Reserved
RO 0x0
7 mmcrxipis
MMC Receive Checksum Offload Interrupt Status

This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared.

This bit is valid only when you select the optional MMC module and Checksum Offload Engine (Type 2) during core configuration.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
6 mmctxis
MMC Transmit Interrupt Status

This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared.

This bit is valid only when you select the optional MMC module during core configuration.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
5 mmcrxis
MMC Receive Interrupt Status

This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared.

This bit is valid only when you select the optional MMC module during core configuration.
Value Description
0x0 DISABLED
0x1 ENABLED
RO 0x0
4 mmcis
MMC Interrupt Status

This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. 

This bit is valid only when you select the optional MMC module during core configuration.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
3 pmtis
PMT Interrupt Status

This bit is set when a Magic packet or Wake-on-LAN frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register.

This bit is valid only when you select the optional PMT module during core configuration.
RO 0x0
2 pcsancis
PCS Auto-Negotiation Complete

This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register.

This bit is valid only when you select the optional TBI, RTBI, or SGMII PHY interface during core configuration and operation.
RO 0x0
1 pcslchgis
PCS Link Status Changed

This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register.
This bit is valid only when you select the optional TBI, RTBI, or SGMII PHY interface during core configuration and operation.
RO 0x0
0 rgsmiiis
RGMII or SMII Interrupt Status

This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Status Register.

This bit is valid only when you select the optional RGMII or SMII PHY interface during core configuration and operation.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0