USR

         UART Status register.
      
Module Instance Base Address Register Address
i_uart_0_uart_address_block 0xFFC02000 0xFFC0207C
i_uart_1_uart_address_block 0xFFC02100 0xFFC0217C

Size: 32

Offset: 0x7C

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_USR_31to5

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_USR_31to5

RO 0x0

RFF

RO 0x0

RFNE

RO 0x0

TFE

RO 0x1

TFNF

RO 0x1

RSVD_BUSY

RO 0x0

USR Fields

Bit Name Description Access Reset
31:5 RSVD_USR_31to5
Reserved bits [31:5] - Read Only
RO 0x0
4 RFF
Receive FIFO Full.
This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
receive FIFO is completely full. That is:
0 = Receive FIFO not full
1 = Receive FIFO Full
This bit is cleared when the RX FIFO is no longer full.
Value Description
0x0 Receive FIFO not full
0x1 Receive FIFO full
RO 0x0
3 RFNE
Receive FIFO Not Empty.
This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
receive FIFO contains one or more entries.
0 = Receive FIFO is empty
1 = Receive FIFO is not empty
This bit is cleared when the RX FIFO is empty.
Value Description
0x0 Receive FIFO is empty
0x1 Receive FIFO is not empty
RO 0x0
2 TFE
Transmit FIFO Empty.
This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
transmit FIFO is completely empty.
0 = Transmit FIFO is not empty
1 = Transmit FIFO is empty
This bit is cleared when the TX FIFO is no longer empty.
Value Description
0x0 Transmit FIFO is not empty
0x1 Transmit FIFO is empty
RO 0x1
1 TFNF
Transmit FIFO Not Full.
This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
transmit FIFO in not full.
0 = Transmit FIFO is full
1 = Transmit FIFO is not full
This bit is cleared when the TX FIFO is full.
Value Description
0x0 Transmit FIFO is full
0x1 Transmit FIFO is not full
RO 0x1
0 RSVD_BUSY
UART Busy.
This bit is only valid when UART_16550_COMPATIBLE == NO. This indicates that a serial
transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive.
0 - DW_apb_uart is idle or inactive
1 - DW_apb_uart is busy (actively transferring data)
Note that it is possible for the UART Busy bit to be cleared even though a new
character may have been sent from another device. That is, if the DW_apb_uart
has no data in the THR and RBR and there is no transmission in progress and a start
bit of a new character has just reached the DW_apb_uart. This is due to the fact
that a valid start is not seen until the middle of the bit period and this duration
is dependent on the baud divisor that has been programmed. If a second system clock
has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also be
delayed by several cycles of the slower clock.
Value Description
0x0 DW_apb_uart is idle or inactive
0x1 DW_apb_uart is busy (actively transferring data)
RO 0x0