DMATDLR

         DMA Transmit Data Level.
This register is only valid when the DW_apb_ssi is configured with a set
of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not
configured for DMA operation, this register will not exist and writing
to its address will have no effect; reading from its address will
return zero.
      
Module Instance Base Address Register Address
i_spim_0_ssi_address_block 0xFFDA4000 0xFFDA4050
i_spim_1_ssi_address_block 0xFFDA5000 0xFFDA5050

Size: 32

Offset: 0x50

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_DMATDLR

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_DMATDLR

RO 0x0

DMATDL

RW 0x0

DMATDLR Fields

Bit Name Description Access Reset
31:8 RSVD_DMATDLR
Reserved bits - Read Only
RO 0x0
7:0 DMATDL
Transmit Data Level.
This bit field controls the level at which a DMA request is made by the
transmit logic. It is equal to the watermark level; that is, the
dma_tx_req signal is generated when the number of valid data entries
in the transmit FIFO is equal to or below this field value, and TDMAE = 1.
RW 0x0