ERRINTEN 

         Error Interrupt enable
Module Instance Base Address Register Address
soc_hmc_adp_csr_inst_0_ocp_slv_block 0xF8011000 0xF8011110

Size: 32

Offset: 0x110

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

SEQ2CORE_INTREN

0x0

HMI_INTREN

0x0

DERRINTEN

0x0

SERRINTEN

0x0

ERRINTEN Fields

Bit Name Description Access Reset
3 SEQ2CORE_INTREN 
Enables seq2core interrupt.
1'b0: seq2core interrupt generation logic is disabled.
1'b1: seq2core interrupt generation logic is enabled.
Value Description
0 DISABLE
1 ENABLE
RW 0x0
2 HMI_INTREN 
Enables GP HMI interrupt.
This bit is used to enable the general purpose HMI interrupt error interrupt to system manager. When this bit is enabled along with autoWB_drop_en, it compares the internal counter with autoWB_drop_cntreg value. If the value is greater than or equal to, then the interrupt will be asserted..
1'b0: hmi interrupt generation logic is disabled.
1'b1: hmi interrupt generation logic is enabled.
Value Description
0 DISABLE
1 ENABLE
RW 0x0
1 DERRINTEN 
This bit is used to enable the double bit error interrupt to system
manager.When dbe error occurs, bus error is always generated with the transaction.DERR interrupt (derr_req)will be generated when this bit is enabled.
1'b0: DBE interrupt generation logic is disabled.
1'b1: DBE interrupt generation logic is enabled,
Value Description
0 DISABLE
1 ENABLE
RW 0x0
0 SERRINTEN 
This bit is used to enable the single bit error to system manager. It enables the interrupt modes (sbe request,compare match)
1'b0: SBE interrupt generation logic is disabled.
1'b1: SBE interrupt generation logic is enabled,
Value Description
0 DISABLE
1 ENABLE
RW 0x0