cache_read_enable

         Device supports cache read command sequence 
      
Module Instance Base Address Register Address
i_nand_config 0xFFB80000 0xFFB800B0

Size: 32

Offset: 0xB0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

flag

RW 0x0

cache_read_enable Fields

Bit Name Description Access Reset
0 flag
[list][*]1 - Cache read supported [*]0 - Cache read not supported[/list] 
RW 0x0