dma_periph

         Controls the security state of a peripheral request interface. Sampled by the DMA controller when it exits from reset.
These register bits should be updated during system initialization prior to removing the DMA controller from reset. They may not be changed dynamically during DMA operation.

Module Instance	Base Address	Register Address
`i_sys_mgr_core`	`0xFFD12000`	`0xFFD12024`

Size: 32

Offset: 0x24

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`ns` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ns` `RW 0x0`

dma_periph Fields

Bit	Name	Description	Access	Reset
31:0	`ns`	If bit index [x] is 0, the DMA controller assigns peripheral request interface x to the Secure state. If bit index [x] is 1, the DMA controller assigns peripheral request interface x to the Non-secure state. Reset by a cold or warm reset.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:0

ns

If bit index [x] is 0, the DMA controller assigns peripheral request interface x to the Secure state.
If bit index [x] is 1, the DMA controller assigns peripheral request interface x to the Non-secure state.
Reset by a cold or warm reset.

RW

0x0