SER

         Slave Enable Register.
This register is valid only when the DW_apb_ssi is configured as a master
device. When the DW_apb_ssi is configured as a serial slave, writing to
this location has no effect; reading from this location returns 0. The
register enables the individual slave select output lines from the
DW_apb_ssi master. Up to 16 slave-select output pins are available on the
DW_apb_ssi master. You cannot write to this register when DW_apb_ssi is
busy and when SSI_EN = 1.

Module Instance	Base Address	Register Address
`i_spim_0_ssi_address_block`	`0xFFDA4000`	`0xFFDA4010`
`i_spim_1_ssi_address_block`	`0xFFDA5000`	`0xFFDA5010`

Size: 32

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_SER` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_SER` `RO 0x0`												`SER` `RW 0x0`

SER Fields

Bit

Name

Description

Access

Reset

31:4

RSVD_SER

Reserved bits - Read Only

RO

0x0

3:0

SER

Slave Select Enable Flag.
Each bit in this register corresponds to a slave select line (ss_x_n)
from the DW_apb_ssi master. When a bit in this register is set (1), the
corresponding slave select line from the master is activated when a
serial transfer begins. It should be noted that setting or clearing bits
in this register have no effect on the corresponding slave select outputs
until a transfer is started. Before beginning a transfer, you should
enable the bit in this register that corresponds to the slave device
with which the master wants to communicate. When not operating in
broadcast mode, only one bit in this field should be set.
1: Selected
0: Not Selected

Value	Description
0x0	No slave selected
0x1	Slave is selected

RW

0x0