devwr

         
      
Module Instance Base Address Register Address
i_qspi_qspiregs 0xFF8D2000 0xFF8D2008

Size: 32

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

wr_instr_resv4_fld

RO 0x0

dummywrclks

RW 0x0

wr_instr_resv3_fld

RO 0x0

datawidth

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

wr_instr_resv2_fld

RO 0x0

addrwidth

RW 0x0

wr_instr_resv1_fld

RO 0x0

wropcode

RW 0x2

devwr Fields

Bit Name Description Access Reset
31:29 wr_instr_resv4_fld


                     
RO 0x0
28:24 dummywrclks
 Number of dummy clock cycles required by device for write instruction. 
RW 0x0
23:18 wr_instr_resv3_fld


                     
RO 0x0
17:16 datawidth
 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs. 
Value Description
0 Write data transferred on DQ0. Supported by all SPI flash devices
1 Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
2 Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.
RW 0x0
15:14 wr_instr_resv2_fld


                     
RO 0x0
13:12 addrwidth
 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3 
Value Description
0 Write address transferred on DQ0. Supported by all SPI flash devices
1 Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
2 Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.
RW 0x0
11:8 wr_instr_resv1_fld


                     
RO 0x0
7:0 wropcode
 Write Opcode 
RW 0x2