IC_TX_TL

         Name: I2C Transmit FIFO Threshold Register
Size: 8 bits
Address Offset: 0x3c
Read/Write Access: Read/Write
      
Module Instance Base Address Register Address
i_i2c_emac_0_DW_apb_i2c_addr_block1 0xFFC02A00 0xFFC02A3C
i_i2c_emac_1_DW_apb_i2c_addr_block1 0xFFC02B00 0xFFC02B3C
i_i2c_emac_2_DW_apb_i2c_addr_block1 0xFFC02C00 0xFFC02C3C

Size: 32

Offset: 0x3C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IC_TX_TL

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_IC_TX_TL

RO 0x0

TX_TL

RW 0x0

IC_TX_TL Fields

Bit Name Description Access Reset
31:8 RSVD_IC_TX_TL
Reserved bits - Read Only
RO 0x0
7:0 TX_TL
Transmit FIFO Threshold Level
Controls the level of entries (or below) that trigger
the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register).
The valid range is 0-255, with the additional restriction that
it may not be set to value larger than the depth of the buffer.
If an attempt is made to do that, the actual value set will be
the maximum depth of the buffer.
A value of 0 sets the threshold for 0 entries, and a value of 255
sets the threshold for 255 entries.
Reset value: IC_TX_TL configuration parameter
RW 0x0