SMMU_NSACR

         Provides IMPLEMENTATION DEFINED functionality.

Note: For register and programming information, please refer to the ARM CoreLink MMU System Memory Management Unit Technical Reference Manual.

Module Instance	Base Address	Register Address
`i_aps_smmu_secure_registers`	`0xFA000000`	`0xFA000410`

Size: 32

Offset: 0x410

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`					`CACHE_LOCK` `RW 0x1`	`DP4K_TBUDISB` `RW 0x0`	`DP4K_TCUDISB` `RW 0x0`	`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`					`S2CRB_TLBEN` `RW 0x0`	`MMUDISB_TLBEN` `RW 0x0`	`SMTNMB_TLBEN` `RW 0x0`	`Reserved`			`IPA2PA_CEN` `RW 0x1`	`S2WC2EN` `RW 0x1`	`S1WC2EN` `RW 0x1`	`Reserved`