cfg

         
      
Module Instance Base Address Register Address
i_qspi_qspiregs 0xFF8D2000 0xFF8D2000

Size: 32

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

idle

RO 0x1

config_resv2_fld

RO 0x0

bauddiv

RW 0xF

enterxipimm

RW 0x0

enterxipnextrd

RW 0x0

enahbremap

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

endma

RW 0x0

wp

RW 0x0

percslines

RW 0x0

perseldec

RW 0x0

enlegacyip

RW 0x0

endiracc

RW 0x0

config_resv1_fld

RO 0x0

selclkphase

RW 0x0

selclkpol

RW 0x0

en

RW 0x0

cfg Fields

Bit Name Description Access Reset
31 idle
 This is a STATUS read-only bit. Note this is a retimed signal, so there will be some inherent delay on the generation of this status signal. 
Value Description
0 Non-Idle Mode
1 Idle Mode
RO 0x1
30:23 config_resv2_fld


                     
RO 0x0
22:19 bauddiv
SPI baud rae = (master reference clock) baud_rate_divisor
Value Description
0 Baud Rate Div/2
1 Baud Rate Div/4
2 Baud Rate Div/6
3 Baud Rate Div/8
4 Baud Rate Div/10
5 Baud Rate Div/12
6 Baud Rate Div/14
7 Baud Rate Div/16
8 Baud Rate Div/18
9 Baud Rate Div/20
10 Baud Rate Div/22
11 Baud Rate Div/24
12 Baud Rate Div/26
13 Baud Rate Div/28
14 Baud Rate Div/30
15 Baud Rate Div/32
RW 0xF
18 enterxipimm
 Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the external device wakes up in XIP mode (as per the contents of its non- volatile configuration register). The controller will assume the next READ instruction will be passed to the device as an XIP instruction, and therefore will not require the READ opcode to be transferred. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only after the next READ instruction is executed. Software therefore should ensure that at least one READ instruction is requested after resetting this bit in order to be sure that XIP mode is exited. 
Value Description
0 Exit XIP Mode on next READ instruction
1 Enter XIP Mode immediately
RW 0x0
17 enterxipnextrd
 Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled, then setting to ?1? will inform the controller that the device is ready to enter XIP on the next READ instruction. The controller will therefore send the appropriate command sequence, including mode bits to cause the device to enter XIP mode. Use this register after the controller has ensured the FLASH device has been configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only AFTER the next READ instruction is executed. Software should therefore ensure that at least one READ instruction is requested after resetting this bit before it can be sure XIP mode in the device is exited. 
Value Description
0 Exit XIP Mode on next READ instruction
1 Enter XIP Mode on next READ instruction
RW 0x0
16 enahbremap
 (Direct Access Mode Only) When set to 1, the incoming AHB address will be adapted and sent to the FLASH device as (address + N), where N is the value stored in the remap address register. 
Value Description
0 Disable AHB Re-mapping
1 Enable AHB Re-mapping
RW 0x0
15 endma
 Set to 1 to enable the DMA handshaking logic. When enabled the QSPI will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable 
Value Description
0 Disable DMA Mode
1 Enable DMA Mode
RW 0x0
14 wp
 Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary. 
Value Description
0 Disable Write Protect
1 Enable Write Protect
RW 0x0
13:10 percslines
 Peripheral chip select lines If pdec = 0, ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 (no peripheral selected) else ss[3:0] directly drives n_ss_out[3:0] 
RW 0x0
9 perseldec
 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode (n_ss_out = ss) 
Value Description
0 Selects 1 of 4 qspi_n_ss_out[3:0]
1 Select external 4-to-16 decode
RW 0x0
8 enlegacyip
 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode, any  write to the controller via the AHB interface is serialized and sent to the FLASH device.  Any valid AHB read will pop the internal RX-FIFO, retrieving data that was forwarded by the external FLASH device on the SPI lines,4,2 or 1 byte transfers are permitted and controlled via the HSIZE input. 
Value Description
0 Use Direct/Indirect Access Controller
1 Legacy Mode
RW 0x0
7 endiracc
 0 : disable the Direct Access Controller once current transfer of the data word (FF_W) is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access Controller are both disabled, all AHB requested are completed with an error response. 
Value Description
0 Disable Direct Access Ctrl
1 Enable Direct Access Ctrl
RW 0x0
6:3 config_resv1_fld


                     
RO 0x0
2 selclkphase
 Selects whether the clock is in an active or inactive phase outside the SPI word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word 
Value Description
0 SPI clock is quiescent low
1 Clock Inactive
RW 0x0
1 selclkpol
 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high 
Value Description
0 SPI clock is quiescent high
1 SPI clock is quiescent low
RW 0x0
0 en
 0 : disable the QSPI once current transfer of the data word (FF_W) is complete. 1 : enable the QSPI When spi_enable = 0, all output enables are inactive and all pins are set to input mode. 
Value Description
0 Disable the QSPI
1 Enable the QSPI
RW 0x0