fpgaintf_en_3

         Used to disable individual interfaces between the FPGA and HPS.
This register is reset only on a cold reset (ignores warm reset).

Module Instance	Base Address	Register Address
`i_sys_mgr_core`	`0xFFD12000`	`0xFFD12070`

Size: 32

Offset: 0x70

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`															`emac_2` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`emac_1` `RW 0x0`	`Reserved`							`emac_0` `RW 0x0`

fpgaintf_en_3 Fields

Bit

Name

Description

Access

Reset

emac_2

Used to disable signals from the FPGA fabric to the EMAC modules that could potentially interfere with their normal operation.
The array index corresponds to the EMAC module instance.

Value	Description
0	Disable
1	Enable

RW

0x0

emac_1

Used to disable signals from the FPGA fabric to the EMAC modules that could potentially interfere with their normal operation.
The array index corresponds to the EMAC module instance.

Value	Description
0	Disable
1	Enable

RW

0x0

emac_0

Used to disable signals from the FPGA fabric to the EMAC modules that could potentially interfere with their normal operation.
The array index corresponds to the EMAC module instance.

Value	Description
0	Disable
1	Enable

RW

0x0