IC_FS_SCL_HCNT

         Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
Size: 16 bits
Address Offset: 0x1c
Read/Write Access: Read/Write
Dependencies: This register is not applicable  when IC_ULTRA_FAST_MODE=1

      
Module Instance Base Address Register Address
sdm_i_i2c_0_DW_apb_i2c_addr_block1 0xFF8D0100 0xFF8D011C
sdm_i_i2c_1_DW_apb_i2c_addr_block1 0xFF8D0200 0xFF8D021C

Size: 32

Offset: 0x1C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IC_FS_SCL_HCNT

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IC_FS_SCL_HCNT

RW 0x4B

IC_FS_SCL_HCNT Fields

Bit Name Description Access Reset
31:16 RSVD_IC_FS_SCL_HCNT
Reserved bits - Read Only
RO 0x0
15:0 IC_FS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to
ensure proper I/O timing. This register sets the SCL clock high-period
count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code
and START BYTE or General CALL. 
This register goes away and becomes read-only returning 0s if
IC_MAX_SPEED_MODE = standard. This register can be written only
when the I2C interface is disabled, which corresponds to the IC_ENABLE[0]
register being set to 0. Writes at other times have no effect.
The minimum valid value is 6; hardware prevents values less than this
being written, and if attempted results in 6 being set. For designs with
APB_DATA_WIDTH == 8 the order of programming is important to
ensure the correct operation of the DW_apb_i2c. The lower byte must be
programmed first. Then the upper byte is programmed.
When the configuration parameter IC_HC_COUNT_VALUES is set to 1,
this register is read only.
Reset value: IC_FS_SCL_HIGH_COUNT configuration parameter
RW 0x4B