DATA

         Provides read/write access to data FIFO. Addresses 0x200 and above are mapped to the data FIFO. More than one address is mapped to data FIFO so that FIFO can be accessed using bursts.
      
Module Instance Base Address Register Address
i_sdmmc_sdmmc_block_1 0xFF8D1000 0xFF8D1200

Size: 32

Offset: 0x200

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

value

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

value

RW 0x0

DATA Fields

Bit Name Description Access Reset
31:0 value
Provides read/write access to data FIFO.
RW 0x0