SRBR0

         Shadow Receive Buffer Register
      
Module Instance Base Address Register Address
i_uart_0_uart_address_block 0xFFC02000 0xFFC02030
i_uart_1_uart_address_block 0xFFC02100 0xFFC02130

Size: 32

Offset: 0x30

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_SRBR0_31to8

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_SRBR0_31to8

RO 0x0

srbr0

RO 0x0

SRBR0 Fields

Bit Name Description Access Reset
31:8 RSVD_SRBR0_31to8
Reserved bits [31:8] - Read Only
RO 0x0
7:0 srbr0
Shadow Receive Buffer Register 0:
This is a shadow register for the RBR and has been allocated sixteen 32-bit locations
so as to accommodate burst accesses from the master.
This register contains the data byte received on the serial input port (sin) in UART
mode or the serial infrared input (sir_in) in infrared mode. The data in this register
is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set.
If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the
data in the RBR must be read before the next data arrives, otherwise it will be
overwritten, resulting in an overrun error.
If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this
register accesses the head of the receive FIFO. If the receive FIFO is full and this
register is not read before the next data character arrives, then the data already
in the FIFO will be preserved but any incoming data will be lost. An overrun error
will also occur.
RO 0x0