SMMU_CB5_PMCR

         Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
      
Note: For register and programming information, please refer to the ARM CoreLink MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA025F04

Size: 32

Offset: 0x25F04

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IMP

RO 0x0

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

X

RW 0x0

Reserved

P

RO 0x0

E

RW 0x0