CTRLR0

Reserved bits - Read Only

SPI Frame Format:
Selects data frame format for Transmitting/Receiving the data 

00 - Standard SPI Format 

01 - Dual SPI Format 

10 - Quad SPI Format 

Bits only valid when SSI_SPI_MODE is either set to “Dual” or “Dual/Quad Both” mode.

Data Frame Size in 32-bit transfer size mode.
Selects the data frame length. When the data frame size is programmed
to be less than 32 bits, the receive data are automatically
right-justified by the receive logic, with the upper bits of the receive
FIFO zero-padded. You must right-justify transmit data before writing
into the transmit FIFO. The transmit logic ignores the upper unused
bits when transmitting the data

Note: When SSI_SPI_MODE is either set to “Dual” or “Dual/Quad Both” mode and  SPI_FRF  is not set to 2’b00. 
 
DFS value should be multiple of 2 if SPI_FRF = 01, and 

DFS value should be multiple of 4 if SPI_FRF = 10.

Control Frame Size. Selects the length of the control word for the
Microwire frame format

When SSI_SPI_MODE is either set to “Dual” or “Dual/Quad Both” mode and  SPI_FRF  is not set to 2’b00.
This bit defines Length of Address to be transmitted. Refer Table 4 6 for field decode. 
Only after this much bits are programmed in to the FIFO the transfer can begin.

Shift Register Loop. Used for testing purposes only. When internally
active, connects the transmit shift register output to the receive 

shift register input. 

0 - Normal Mode Operation 

1 - Test Mode Operation

Reserved field- Read-only

Transfer Mode.
Selects the mode of transfer for serial communication. This field does
not affect the transfer duplicity. Only indicates whether the receive or
transmit data are valid. In transmit-only mode, data received from the
external device is not valid and is not stored in the receive FIFO memory;
it is overwritten on the next transfer. In receive-only mode, transmitted
data are not valid. After the first write to the transmit FIFO, the same
word is retransmitted for the duration of the transfer. In
transmit-and-receive mode, both transmit and receive data are valid.
The transfer continues until the transmit FIFO is empty. Data received
from the external device are stored into the receive FIFO memory, where
it can be accessed by the host processor. 

00 - Transmit & Receive 

01 - Transmit Only 

10 - Receive Only 

11 - EEPROM Read 

When SSI_SPI_MODE is either set to “Dual” or “Dual/Quad Both” mode and  SPI_FRF  is not set to 2’b00. 
There are only two valid combinations: 

01  Read 

10 - Write

Serial Clock Polarity.
Valid when the frame format (FRF) is set to Motorola SPI. Used to select
the polarity of the inactive serial clock, which is held inactive when
the DW_apb_ssi master is not actively transferring data on the serial bus. 

0 - Inactive state of serial clock is low 

1 - Inactive state of serial clock is high

Serial Clock Phase.
Valid when the frame format (FRF) is set to Motorola SPI. The serial
clock phase selects the relationship of the serial clock with the slave
select signal. When SCPH = 0, data are captured on the first edge of
the serial clock. When SCPH = 1, the serial clock starts toggling one
cycle after the slave select line is activated, and data are captured
on the second edge of the serial clock. 

0: Serial clock toggles in middle of first data bit 

1: Serial clock toggles at start of first data bit

Frame Format.
Selects which serial protocol transfers the data. 

00 - Motorola SPI 

01 - Texas Instruments SSP 

10 - National Semiconductors Microwire 

11 - Reserved

Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is
configured to 16. If SSI_MAX_XFER_SIZE is configured to 32, then writing to this field
will not have any effect.
Selects the data frame length. When the data frame size is programmed to be less than
16 bits, the receive data are automatically right-justified by the receive logic, with the
upper bits of the receive FIFO zero-padded.
You must right-justify transmit data before writing into the transmit FIFO. The transmit
logic ignores the upper unused bits when transmitting the data 

Note: When SSI_SPI_MODE is either set to “Dual” or “Dual/Quad Both” mode and  SPI_FRF  is not set to 2’b00. 
 
DFS value should be multiple of 2 if SPI_FRF = 01, and 

DFS value should be multiple of 4 if SPI_FRF = 10.