gmacgrp_sgmii_rgmii_smii_control_status

         
The SGMII/RGMII/SMII Status register indicates the status signals received by the RGMII interface (selected at reset) from the PHY.
      
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF8000D8
i_emac_emac1 0xFF802000 0xFF8020D8
i_emac_emac2 0xFF804000 0xFF8040D8

Size: 32

Offset: 0xD8

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

lnksts

RO 0x0

lnkspeed

RO 0x0

lnkmod

RO 0x0

gmacgrp_sgmii_rgmii_smii_control_status Fields

Bit Name Description Access Reset
3 lnksts
This bit indicates whether the link is up (1'b1) or down (1'b0).
Value Description
0x0 LINKDOWN
0x1 LINKUP
RO 0x0
2:1 lnkspeed
This bit indicates the current speed of the link. Bit 2 is reserved when the MAC is configured for the SMII PHY interface.
Value Description
0x0 SPEED2POINT5MHZ
0x1 SPEED25MHZ
0x2 SPEED125MHZ
RO 0x0
0 lnkmod
This bit indicates the current mode of operation of the link
Value Description
0x0 HALFDUP
0x1 FULLDUP
RO 0x0