ecc_intmask_clr

         Write 1 to Clear a specific modules interrupt mask.
Reads should not return an error, but the actual read value is "Undefined" .
      
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD12000 0xFFD12098

Size: 32

Offset: 0x98

Access: WO

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

ddr1

WO 0x0

ddr0

WO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

sdmmcb

WO 0x0

sdmmca

WO 0x0

nand_rd

WO 0x0

nand_wr

WO 0x0

nand_buf

WO 0x0

dma

WO 0x0

emac2_tx

WO 0x0

emac2_rx

WO 0x0

emac1_tx

WO 0x0

emac1_rx

WO 0x0

emac0_tx

WO 0x0

emac0_rx

WO 0x0

usb1

WO 0x0

usb0

WO 0x0

ocram

WO 0x0

Reserved

ecc_intmask_clr Fields

Bit Name Description Access Reset
17 ddr1


                     
WO 0x0
16 ddr0


                     
WO 0x0
15 sdmmcb


                     
WO 0x0
14 sdmmca


                     
WO 0x0
13 nand_rd


                     
WO 0x0
12 nand_wr


                     
WO 0x0
11 nand_buf


                     
WO 0x0
10 dma


                     
WO 0x0
9 emac2_tx


                     
WO 0x0
8 emac2_rx


                     
WO 0x0
7 emac1_tx


                     
WO 0x0
6 emac1_rx


                     
WO 0x0
5 emac0_tx


                     
WO 0x0
4 emac0_rx


                     
WO 0x0
3 usb1


                     
WO 0x0
2 usb0


                     
WO 0x0
1 ocram


                     
WO 0x0