CLKDIV

         Clock Divider Register
      
Module Instance Base Address Register Address
i_sdmmc_sdmmc_block_1 0xFF8D1000 0xFF8D1008

Size: 32

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CLK_DIVIDER3

RO 0x0

CLK_DIVIDER2

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CLK_DIVIDER1

RO 0x0

CLK_DIVIDER0

RW 0x0

CLKDIV Fields

Bit Name Description Access Reset
31:24 CLK_DIVIDER3
Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of “ff” means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.
RO 0x0
23:16 CLK_DIVIDER2
Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of “ff” means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.
RO 0x0
15:8 CLK_DIVIDER1
Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of “ff” means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported
RO 0x0
7:0 CLK_DIVIDER0
Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of “ff” means divide by 2*255 = 510, and so on.
RW 0x0