dmagrp_receive_interrupt_watchdog_timer

         <b> Register 9 (Receive Interrupt Watchdog Timer Register) </b>

This register, when written with non-zero value, enables the watchdog timer for the Receive Interrupt (Bit 6) of Register 5 (Status Register)
      
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF801024
i_emac_emac1 0xFF802000 0xFF803024
i_emac_emac2 0xFF804000 0xFF805024

Size: 32

Offset: 0x1024

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_8

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_31_8

RO 0x0

riwt

RW 0x0

dmagrp_receive_interrupt_watchdog_timer Fields

Bit Name Description Access Reset
31:8 reserved_31_8
Reserved
RO 0x0
7:0 riwt
RI Watchdog Timer Count

This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame.
RW 0x0