IIR

         Interrupt Identification Register
      
Module Instance Base Address Register Address
i_uart_uart_address_block 0xFF8D0000 0xFF8D0008

Size: 32

Offset: 0x8

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IIR_31to8

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_IIR_31to8

RO 0x0

FIFOSE

RO 0x0

RSVD_IIR_5to4

RO 0x0

IID

RO 0x1

IIR Fields

Bit Name Description Access Reset
31:8 RSVD_IIR_31to8
Reserved bits [31:8] - Read Only
RO 0x0
7:6 FIFOSE
Bits[7:6], FIFO's Enabled (or FIFOSE):
This is used to indicate whether the FIFO's are enabled or disabled.
00 = disabled.
11 = enabled
Value Description
0x0 FIFOs are disabled
0x3 FIFOs are enabled
RO 0x0
5:4 RSVD_IIR_5to4
Reserved bits [5:4] - Read Only
RO 0x0
3:0 IID
Bits[3:0], Interrupt ID (or IID):
This indicates the highest priority pending interrupt which can be one of the
following types:
0000 = modem status.
0001 = no interrupt pending.
0010 = THR empty.
0100 = received data available.
0110 = receiver line status.
0111 = busy detect.
1100 = character timeout.
Note, an interrupt of type 0111 (busy detect) will never get indicated if
UART_16550_COMPATIBLE == YES in coreConsultant.
Value Description
0xc character timeout
0x0 modem status
0x1 no interrupt pending
0x2 THR empty
0x4 received data available
0x5 receiver line status
0x7 busy detect
RO 0x1