ERRINTEN

         Error Interrupt enable
      
Module Instance Base Address Register Address
ecc_emac0_tx_ecc_registerBlock 0xFF8C0400 0xFF8C0410

Size: 32

Offset: 0x10

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

SERRINTEN

0x0

ERRINTEN Fields

Bit Name Description Access Reset
0 SERRINTEN
This bit is used to enable single bit error interrupt of ECC RAM system
Value Description
0 DISABLE
1 ENABLE
RW 0x0