SMMU_SIDR0

         Provides SMMU capability information.
      
Note: For register and programming information, please refer to the ARM CoreLink MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA000020

Size: 32

Offset: 0x20

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SES

RO 0x1

S1TS

RO 0x1

S2TS

RO 0x1

NTS

RO 0x1

SMS

RO 0x1

ATOSNS

RO 0x1

PTFS

RO 0x0

NUMIRPT

RO 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

CTTW

RO 0x0

BTM

RO 0x1

NUMSIDB

RO 0xF

Reserved

NUMSMRG

RO 0x40