pin26sel

         HPS Pinmux Select for IO2
      
Module Instance Base Address Register Address
i_dedio_pinmux_csr 0xFFD13000 0xFFD13068

Size: 32

Offset: 0x68

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

val

RW 0x8

pin26sel Fields

Bit Name Description Access Reset
3:0 val
Select value determines which interface has been selected for IO2. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9.
0000 (0) -- Pin connected to emac1.rx_clk
0001 (1) -- NA
0010 (2) -- Pin connected to trace.d8
0011 (3) -- Pin connected to nand.we_n
0100 (4) -- Pin connected to i2c0.sda
0101 (5) -- Pin connected to uart0.tx
0110 (6) -- Pin connected to cm.pll_clk2
0111 (7) -- Pin connected to spim1.miso
1000 (8) -- Pin connected to gpio1.io2
1001 (9) -- Pin connected to cm.hps_osc_clk
RW 0x8