PeriphPll_grp Address Map

Contains registers with settings for the Peripheral PLL.

Module Instance	Base Address	End Address
`i_clk_mgr_perpllgrp`	`0xFFD1007C`	`0xFFD100CF`

Register	Offset	Width	Access	Reset Value	Description
`en`	`0x0`	`32`	`RW`	`0x00000FFF`	Enable Register
`ens`	`0x4`	`32`	`RW`	`0x00000800`	Enable Set Register
`enr`	`0x8`	`32`	`RW`	`0x00000800`	Enable Reset Register
`bypass`	`0xC`	`32`	`RW`	`0x000000FF`	Bypass Register
`bypasss`	`0x10`	`32`	`RW`	`0x000000FF`	Bypass Set Register
`bypassr`	`0x14`	`32`	`RW`	`0x000000FF`	Bypass Reset Register
`emacctl`	`0x18`	`32`	`RW`	`0x00000000`	Main Divide Register
`gpiodiv`	`0x1C`	`32`	`RW`	`0x00000001`	GPIO Divide Register
`pllglob`	`0x20`	`32`	`RW`	`0x14000101`	This refects register settings for all clock channels of peripheral PLL.
`fdbck`	`0x24`	`32`	`RW`	`0x22000000`	VCO freq register counters
`mem`	`0x28`	`32`	`RW`	`0x00000000`	Registers dealing with PLL internal memory access.
`memstat`	`0x2C`	`32`	`RW`	`0x00000000`	Periph PLL memstatus register. contains ack and memory read data
`pllc0`	`0x30`	`32`	`RW`	`0x10000002`	Channel C0 frequency settings for the peri PLL
`pllc1`	`0x34`	`32`	`RW`	`0x00000006`	Channel C1 frequency settings for the peri PLL
`vcocalib`	`0x38`	`32`	`RW`	`0x0001085C`	VCO calibration control registers.
`pllc2`	`0x3C`	`32`	`RW`	`0x10000005`	Channel C2 frequency settings for the peri PLL
`pllc3`	`0x40`	`32`	`RW`	`0x0000000C`	Channel C3 frequency settings for the peri PLL
`pllm`	`0x44`	`32`	`RW`	`0x00000060`	Feedback Clock Divider Control (VCO Frequency Register Counters)
`fhop`	`0x48`	`32`	`RW`	`0x00000000`	Frequency Hopping (FHOP)/Dynamic Frequency Scaling(DFS) Control and status register.
`ssc`	`0x4C`	`32`	`RO`	`0x00000000`	Spread Spectrum Clocking (SSC) Control and Status Registers.
`lostlock`	`0x50`	`32`	`RW`	`0x00000000`