firewall_ddr_fpga2sdram_inst_0_scr Address Map

DDR Security Control Registers (SCR)
Module Instance Base Address End Address
soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr 0xF8020100 0xF80201FF
Register Offset Width Access Reset Value Description
enable 0x0 32 RW 0x00000000
Enable
enable_set 0x4 32 WO 0x00000000
Sets Master Region Enable field when written with 1
enable_clear 0x8 32 WO 0x00000000
Clears Master Region Enable field when written with 1
region0addr_base 0x10 32 RW 0x00000000
Base definition for Region 0
region0addr_baseext 0x14 32 RW 0x00000000
base extended definition for Region 0
region0addr_limit 0x18 32 RW 0x0000FFFF
Limit definition for Region 0
region0addr_limitext 0x1C 32 RW 0x00000000
limit extended definition for Region 0
region1addr_base 0x20 32 RW 0x00000000
Base definition for Region 1
region1addr_baseext 0x24 32 RW 0x00000000
base extended definition for Region 1
region1addr_limit 0x28 32 RW 0x0000FFFF
Limit definition for Region 1
region1addr_limitext 0x2C 32 RW 0x00000000
limit extended definition for Region 1
region2addr_base 0x30 32 RW 0x00000000
Base definition for Region 2
region2addr_baseext 0x34 32 RW 0x00000000
base extended definition for Region 2
region2addr_limit 0x38 32 RW 0x0000FFFF
Limit definition for Region 2
region2addr_limitext 0x3C 32 RW 0x00000000
limit extended definition for Region 2
region3addr_base 0x40 32 RW 0x00000000
Base definition for Region 3
region3addr_baseext 0x44 32 RW 0x00000000
base extended definition for Region 3
region3addr_limit 0x48 32 RW 0x0000FFFF
Limit definition for Region 3
region3addr_limitext 0x4C 32 RW 0x00000000
limit extended definition for Region 3