ECCCTRL1

         ECC control 1.
This bit is used to set the initialize the memory and ecc to a known value

Module Instance	Base Address	Register Address
`soc_hmc_adp_csr_inst_0_ocp_slv_block`	`0xF8011000`	`0xF8011100`

Size: 32

Offset: 0x100

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`															`AUTOWB_CNT_RST` `0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`CNT_RST` `0x0`	`Reserved`							`ECC_EN` `0x0`

ECCCTRL1 Fields

Bit

Name

Description

Access

Reset

AUTOWB_CNT_RST

Reset the autoWB internal counter to zero.
1'b0 : No effect on autoWB internal counter. Default value after reset
1'b1 :  Reset the autoWB internal counter to zero

Value	Description
0	STAY
1	RESET

RW

0x0

CNT_RST

Reset of internal counter.
1'b0: No effect on internal counter. Dafault value after reset
1'b1: Reset the internal counter to zero

Value	Description
0	STAY
1	RESET

RW

0x0

ECC_EN

Enable for the ECC detection and correction logic.
1'b0:ECC block is disabled. Default value after reset.
1'b1: ECC block is enabled. Every RAM access will verify the data and generate any necessary error requests.

Value	Description
0	DISABLE
1	ENABLE

RW

0x0