hdskack

         This register includes fields for software to detect the completion of the handshake with certain peripherals. Once the peripheral has completed the handshake, it will set the appropriate bit in this register. Once software has detected that the acknowledge bit is set, it must clear the corresponding request bit in the HDSREQ register.
Software writes 1 to the corresponding bits to clear them.
Fields are reset by a cold reset.
      
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD11000 0xFFD11018

Size: 32

Offset: 0x18

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

debug_l3noc_ack

RW 0x0

l3noc_dbg_ack

RW 0x0

etrstallack

RW 0x0

fpgahsack

RW 0x0

Reserved

mpfe_hmca_drainack

RW 0x0

hdskack Fields

Bit Name Description Access Reset
5 debug_l3noc_ack
This field indicates that L3NOC handshake acknowledge has been received by Reset Manager. A 1 indicates that the L3NOC has acknowledged the handshake request.
The handshake is initiated with L3NOC as a part of handshake request initiated by the DEBUG_L3NOC_REQ field. This handshake is done to stop L3NOC from accepting any new transactions and allow all outstanding transactions to drain. 
RW 0x0
4 l3noc_dbg_ack
This field indicates that L3NOC handshake acknowledge has been received by Reset Manager. A 1 indicates that the L3NOC has acknowledged the handshake request.
The handshake is initiated with L3NOC as a part of warm/watchdog reset assertion sequence or  handshake request initiated by the L3NOC_DBG_REQ field. This handshake is done to stop L3NOC from accepting any new transactions and allow all outstanding transactions to drain. 
RW 0x0
3 etrstallack
This is the acknowlege for a ETR AXI master stall initiated as a part of the ETR handshake.  A 1 indicates that the ETR has stalled its AXI master.
RW 0x0
2 fpgahsack
This is the acknowledge that the FPGA handshake acknowledge has been received by Reset Manager. A 1 indicates that the FPGA has acknowledged the handshake request.
RW 0x0
0 mpfe_hmca_drainack
This is the acknowledge that SDRAM handshake acknowledge has been received by Reset Manager. A 1 indicates that the SDRAM Controller Subsystem has acknowledged the handshake request.
RW 0x0