ISR 

         Interrupt Status Register
Module Instance Base Address Register Address
i_spim_0_ssi_address_block 0xFFDA4000 0xFFDA4030
i_spim_1_ssi_address_block 0xFFDA5000 0xFFDA5030

Size: 32

Offset: 0x30

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_ISR

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_ISR

RO 0x0

MSTIS

RO 0x0

RXFIS

RO 0x0

RXOIS

RO 0x0

RXUIS

RO 0x0

TXOIS

RO 0x0

TXEIS

RO 0x0

ISR Fields

Bit Name Description Access Reset
31:6 RSVD_ISR 
Reserved bits - Read Only
 RO 0x0
5 MSTIS 
Multi-Master Contention Interrupt Status. This bit field is not present
if the DW_apb_ssi is configured as a serial-slave device.
0 = ssi_mst_intr interrupt not active after masking
1 = ssi_mst_intr interrupt is active after masking
Value Description
0x0 Multi-master Contention Interrupt nonactive
0x1 Multi-master Contention Interrupt is active
RO 0x0
4 RXFIS 
Receive FIFO Full Interrupt Status
0 = ssi_rxf_intr interrupt is not active after masking
1 = ssi_rxf_intr interrupt is full after masking
Value Description
0x0 RX FIFO Full Interrupt nonactive
0x1 RX FIFO Full Interrupt is active
RO 0x0
3 RXOIS 
Receive FIFO Overflow Interrupt Status
0 = ssi_rxo_intr interrupt is not active after masking
1 = ssi_rxo_intr interrupt is active after masking
Value Description
0x0 RX FIFO Overflow Interrupt nonactive
0x1 RX FIFO Overflow Interrupt is active
RO 0x0
2 RXUIS 
Receive FIFO Underflow Interrupt Status
0 = ssi_rxu_intr interrupt is not active after masking
1 = ssi_rxu_intr interrupt is active after masking
Value Description
0x0 RX FIFO Underflow Interrupt nonactive
0x1 RX FIFO underflow Interrupt is active
RO 0x0
1 TXOIS 
Transmit FIFO Overflow Interrupt Status
0 = ssi_txo_intr interrupt is not active after masking
1 = ssi_txo_intr interrupt is active after masking
Value Description
0x0 TX FIFO Overflow Interrupt nonactive
0x1 TX FIFO Overflow Interrupt is active
RO 0x0
0 TXEIS 
Transmit FIFO Empty Interrupt Status
0 = ssi_txe_intr interrupt is not active after masking
1 = ssi_txe_intr interrupt is active after masking
Value Description
0x0 TX FIFO Empty Interrupt nonactive
0x1 TX FIFO Empty Interrupt is active
RO 0x0