pin41sel

         HPS Pinmux Select for IO17
      
Module Instance Base Address Register Address
i_dedio_pinmux_csr 0xFFD13000 0xFFD13104

Size: 32

Offset: 0x104

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

val

RW 0x8

pin41sel Fields

Bit Name Description Access Reset
3:0 val
Select value determines which interface has been selected for IO17. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9.
0000 (0) -- Pin connected to emac2.txd1
0001 (1) -- Pin connected to sdmmc.data3
0010 (2) -- Pin connected to trace.d5
0011 (3) -- Pin connected to nand.adq9
0100 (4) -- NA
0101 (5) -- Pin connected to uart1.rts_n
0110 (6) -- NA
0111 (7) -- Pin connected to spim0.ss1_n
1000 (8) -- Pin connected to gpio1.io17
1001 (9) -- Pin connected to cm.hps_osc_clk
RW 0x8