IP_REV_ID

         <p>IP slicon revision ID</p>
      
Module Instance Base Address Register Address
ecc_emac1_tx_ecc_registerBlock 0xFF8C0C00 0xFF8C0C00

Size: 32

Offset: 0x0

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SIREV

RO 0x0

IP_REV_ID Fields

Bit Name Description Access Reset
15:0 SIREV
<p>IP Rev#</p>
<p>These bits indicate the silicon revision number.</p>
RO 0x0