jtag

         Jtag control registers for the  PLLs - Testing Access

Module Instance	Base Address	Register Address
`i_clk_mgr_alteragrp`	`0xFFD100D0`	`0xFFD100D0`

Size: 32

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`rst` `RW 0x1`	`id` `RW 0x80`

jtag Fields

Bit	Name	Description	Access	Reset
8	`rst`	Jtag rst signal. Test reset—will asynchronously reset the JTAG test logic. The logic is reset {with TRST} regardless of the state of TMS or TCLK. (Asynchronous) (Active low reset)	`RW`	`0x1`
7:0	`id`	JTAG ID used to provide each HP PLL IP a unique ID.	`RW`	`0x80`

Bit

Name

Description

Access

Reset

rst

Jtag rst signal.
Test reset—will asynchronously reset the JTAG test logic. The logic is reset {with TRST} regardless of the state of TMS or TCLK.
(Asynchronous) (Active low reset)

RW

0x1

7:0

id

JTAG ID used to provide each HP PLL IP a unique ID.

RW

0x80