DOEPINT3

         Device OUT Endpoint 3 Interrupt Register
      
Module Instance Base Address Register Address
i_usbotg_0_DWC_otg_intreg 0xFFB00000 0xFFB00B68
i_usbotg_1_DWC_otg_intreg 0xFFB40000 0xFFB40B68

Size: 32

Offset: 0xB68

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

StupPktRcvd

RW 0x0

NYETIntrpt

RW 0x0

NAKIntrpt

RW 0x0

BbleErr

RW 0x0

PktDrpSts

RW 0x0

Reserved

BNAIntr

RW 0x0

OutPktErr

RW 0x0

Reserved

Back2BackSETup

RW 0x0

StsPhseRcvd

RW 0x0

OUTTknEPdis

RW 0x0

SetUp

RW 0x0

AHBErr

RW 0x0

EPDisbld

RW 0x0

XferCompl

RW 0x0

DOEPINT3 Fields

Bit Name Description Access Reset
15 StupPktRcvd
Setup Packet Received
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
setup data. There is only one Setup packet per buffer. On receiving a
Setup packet, the DWC_otg core closes the buffer and disables the
corresponding endpoint. The application has to re-enable the endpoint to
receive any OUT data for the Control Transfer and reprogram the buffer
start address.
Note: Because of the above behavior, the DWC_otg core can receive any
number of back to back setup packets and one buffer for every setup
packet is used.
1'b0: No Setup packet received
1'b1: Setup packet received
Reset: 1'b0
Value Description
0x0 No Setup packet received
0x1 Setup packet received
RW 0x0
14 NYETIntrpt
NYET Interrupt (NYETIntrpt)
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Value Description
0x0 No NYET interrupt
0x1 NYET Interrupt
RW 0x0
13 NAKIntrpt
NAK Interrupt (NAKInterrupt)
The core generates this interrupt when a NAK is transmitted or received by the device.
In case of isochronous IN endpoints the interrupt gets generated when a zero length
packet is transmitted due to un-availability of data in the TXFifo.
Value Description
0x0 No NAK interrupt
0x1 NAK Interrupt
RW 0x0
12 BbleErr
NAK Interrupt (BbleErr)
The core generates this interrupt when babble is received for the endpoint.
Value Description
0x0 No BbleErr interrupt
0x1 BbleErr interrupt
RW 0x0
11 PktDrpSts
Packet Drop Status (PktDrpSts)
This bit indicates to the application that an ISOC OUT packet has been dropped. This
bit does not have an associated mask bit and does not generate an interrupt.
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
interrupt feature is selected.
Value Description
0x0 No interrupt
0x1 Packet Drop Status interrupt
RW 0x0
9 BNAIntr
BNA (Buffer Not Available) Interrupt (BNAIntr)
This bit is valid only when Scatter/Gather DMA mode is enabled.
The core generates this interrupt when the descriptor accessed
is not ready For the Core to process, such as Host busy or DMA
done
Value Description
0x0 No BNA interrupt
0x1 BNA interrupt
RW 0x0
8 OutPktErr
OUT Packet Error (OutPktErr)
Applies to OUT endpoints Only
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
core detects an overflow or a CRC error For non-Isochronous
OUT packet.
Value Description
0x0 No OUT Packet Error
0x1 OUT Packet Error
RW 0x0
6 Back2BackSETup
Back-to-Back SETUP Packets Received (Back2BackSETup)
Applies to Control OUT endpoints only.
This bit indicates that the core has received more than three
back-to-back SETUP packets For this particular endpoint. For
information about handling this interrupt,
Value Description
0x0 No Back-to-Back SETUP Packets Received
0x1 Back-to-Back SETUP Packets Received
RW 0x0
5 StsPhseRcvd
Status Phase Received For Control Write (StsPhseRcvd)
This interrupt is valid only For Control OUT endpoints and only in
Scatter Gather DMA mode.
This interrupt is generated only after the core has transferred all
the data that the host has sent during the data phase of a control
write transfer, to the system memory buffer.
The interrupt indicates to the application that the host has
switched from data phase to the status phase of a Control Write
transfer. The application can use this interrupt to ACK or STALL
the Status phase, after it has decoded the data phase. This is
applicable only in Case of Scatter Gather DMA mode.
Value Description
0x0 No Status Phase Received for Control Write
0x1 Status Phase Received for Control Write
RW 0x0
4 OUTTknEPdis
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
Applies only to control OUT endpoints.
Indicates that an OUT token was received when the endpoint
was not yet enabled. This interrupt is asserted on the endpoint
For which the OUT token was received.
Value Description
0x0 No OUT Token Received When Endpoint Disabled
0x1 OUT Token Received When Endpoint Disabled
RW 0x0
3 SetUp
SETUP Phase Done (SetUp)
Applies to control OUT endpoints only.
Indicates that the SETUP phase For the control endpoint is
complete and no more back-to-back SETUP packets were
received For the current control transfer. On this interrupt, the
application can decode the received SETUP data packet.
Value Description
0x0 No SETUP Phase Done
0x1 SETUP Phase Done
RW 0x0
2 AHBErr
AHB Error (AHBErr)
Applies to IN and OUT endpoints.
This is generated only in Internal DMA mode when there is an
AHB error during an AHB read/write. The application can read
the corresponding endpoint DMA address register to get the
error address.
Value Description
0x0 No AHB Error Interrupt
0x1 AHB Error interrupt
RW 0x0
1 EPDisbld
Endpoint Disabled Interrupt (EPDisbld)
Applies to IN and OUT endpoints.
This bit indicates that the endpoint is disabled per the
application's request.
Value Description
0x0 No Endpoint Disabled Interrupt
0x1 Endpoint Disabled Interrupt
RW 0x0
0 XferCompl
Transfer Completed Interrupt (XferCompl)
Applies to IN and OUT endpoints.
 When Scatter/Gather DMA mode is enabled
- For IN endpoint this field indicates that the requested data
from the descriptor is moved from external system memory
to internal FIFO.
- For OUT endpoint this field indicates that the requested
data from the internal FIFO is moved to external system
memory. This interrupt is generated only when the
corresponding endpoint descriptor is closed, and the IOC
bit For the corresponding descriptor is Set.
 When Scatter/Gather DMA mode is disabled, this field
indicates that the programmed transfer is complete on the
AHB as well as on the USB, For this endpoint.
Value Description
0x0 No Transfer Complete Interrupt
0x1 Transfer Complete Interrupt
RW 0x0