mpumodrst 

         The MPUMODRST register is used by software to trigger module resets (individual module reset signals). Writing 1 to any of these fields will cause the CPU core reset signal to be asserted if that CPU is in WFI mode. The Reset Manager hardware will bring the module back out of reset after the appropriate amount of time.
 
All fields are reset by a cold or a warm reset.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD11000 0xFFD11020

Size: 32

Offset: 0x20

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

core3

RW 0x0

core2

RW 0x0

core1

RW 0x0

core0

RW 0x0

mpumodrst Fields

Bit Name Description Access Reset
3 core3 
Resets ncorereset port of CPU3.
 RW 0x0
2 core2 
Resets ncorereset port of CPU2.
 RW 0x0
1 core1 
Resets ncorereset port of CPU1.
 RW 0x0
0 core0 
Resets ncorereset port of CPU0.
 RW 0x0