ocramload
SDM will set this register bit to 1 to indicate that the Onchip RAM content loading is complete. The Reset Manager will wait for this bit to be set before releasing the MPU warm resets.
This Register bit is reset by POR domain only.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_rst_mgr_rstmgr | 0xFFD11000 | 0xFFD11080 |
Size: 32
Offset: 0x80
Access: RW
Access mode: PRIVILEGEMODE
Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
done RW 0x0 |
||||||||||||||
ocramload Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 0 | done |
SDM sets this bit to indicate the Reset Manager that the on chip ram loading is done and it is safe to proceed with the MPU reset de-assertion sequence. |
RW | 0x0 |