rdwr_en_hi_cnt

         Read/Write Enable high pulse width 
      
Module Instance Base Address Register Address
sdm_i_nand_config 0xFFA10000 0xFFA10200

Size: 32

Offset: 0x200

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

value

RW 0xC

rdwr_en_hi_cnt Fields

Bit Name Description Access Reset
4:0 value
Number of clk_x cycles that read or write enable will kept high to meet the min 
                                 Treh/Tweh parameter of the device. The value in this register plus rdwr_en_lo_cnt
                                 register value should meet the min cycle time of the device connected. The default
                                 value is calculated assuming the max clk_x time period of 4ns to work with ONFI
                                 Mode 0 mode of 100ns device cycle time. This assumes a 1x/5x clocking scheme. 
RW 0xC