CLKSRC

         Clock Source Register
      
Module Instance Base Address Register Address
i_sdmmc_sdmmc_block_1 0xFF8D1000 0xFF8D100C

Size: 32

Offset: 0xC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CARD15_CLK_SOURCE

RO 0x0

CARD14_CLK_SOURCE

RO 0x0

CARD13_CLK_SOURCE

RO 0x0

CARD12_CLK_SOURCE

RO 0x0

CARD11_CLK_SOURCE

RO 0x0

CARD10_CLK_SOURCE

RO 0x0

CARD9_CLK_SOURCE

RO 0x0

CARD8_CLK_SOURCE

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CARD7_CLK_SOURCE

RO 0x0

CARD6_CLK_SOURCE

RO 0x0

CARD5_CLK_SOURCE

RO 0x0

CARD4_CLK_SOURCE

RO 0x0

CARD3_CLK_SOURCE

RO 0x0

CARD2_CLK_SOURCE

RO 0x0

CARD1_CLK_SOURCE

RO 0x0

CARD0_CLK_SOURCE

RO 0x0

CLKSRC Fields

Bit Name Description Access Reset
31:30 CARD15_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
29:28 CARD14_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
27:26 CARD13_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
25:24 CARD12_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
23:22 CARD11_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
21:20 CARD10_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
19:18 CARD9_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
17:16 CARD8_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
15:14 CARD7_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
13:12 CARD6_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
11:10 CARD5_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
9:8 CARD4_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
7:6 CARD3_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
5:4 CARD2_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
3:2 CARD1_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0
1:0 CARD0_CLK_SOURCE
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value.
                                                 00  Clock divider 0
                                                 01  Clock divider 1
                                                 10  Clock divider 2
                                                 11  Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
Value Description
0x0 Clock divider 0
0x1 Clock divider 1
0x2 Clock divider 2
0x3 Clock divider 3
RO 0x0