HCFG

Mode Change Ready Timer Enable (ModeChTimEn)
This bit is used to enable/disable the Host core 
to wait  200 PHY clock cycles at the end of Resumeto change the opmode signal to the PHY to 00 
after Suspend or LPM.
1'b0 : The Host core waits for either 200 PHY clock cycles or a linestate 
of SE0 at the end of resume to the change the opmode from 2'b10 to 2'b00
1'b1 : The Host core waits only for a linstate of SE0 at the end of resume
to change the opmode from 2'b10 to 2'b00.

RESERVED

Enable Periodic Scheduling (PerSchedEna):
Applicable in host DDMA mode only.
Enables periodic scheduling within the core. Initially, the bit is reset.
The core will not process any periodic channels. As soon as this bit is set,
the core will get ready to start scheduling periodic channels and 
sets HCFG.PerSchedStat. The setting of HCFG.PerSchedStat indicates the core
has enabled periodic scheduling. Once HCFG.PerSchedEna is set, 
the application is not supposed to again reset the bit unless HCFG.PerSchedStat
is set. As soon as this bit is reset, the core will get ready to
stop scheduling periodic channels and resets HCFG.PerSchedStat.

Frame List Entries(FrListEn). The value in the register specifies the number 
of entries in the Frame list.
This field is valid only in Scatter/Gather DMA mode.
2'b00: 8 Entries 
2'b01: 16 Entries
2'b10: 32 Entries
2'b11: 63 Entries

Enable Scatter/gather DMA in Host mode (DescDMA). 
When the Scatter/Gather DMA option selected during configuration 
of the RTL, the application can set this bit during initialization
to enable the Scatter/Gather DMA operation.
NOTE: This bit must be modified only once after a reset.
 \The following combinations are available for programming:
GAHBCFG.DMAEn=0,HCFG.DescDMA=0 => Slave mode 
GAHBCFG.DMAEn=0,HCFG.DescDMA=1 => Invalid
GAHBCFG.DMAEn=1,HCFG.DescDMA=0 => Buffered DMA mode 
GAHBCFG.DMAEn=1,HCFG.DescDMA=1 => Scatter/Gather DMA mode

RESERVED

Resume Validation Period  (ResValid)
This field is effective only when HCFG.Ena32KHzS is set.
It will control the resume period when the core resumes from suspend. 
The core counts for 'ResValid' number of clock cycles to detect a 
valid resume when this is set.

Enable 32 KHz Suspend mode (Ena32KHzS)
This bit can be set only in FS PHY interface is selected. 
Else, this bit needs to be set to zero. 
When FS PHY interface is chosen and this bit is set, 
the core expects that the PHY clock during Suspend is switched 
from 48 MHz to 32 KHz.

RESERVED

FS- and LS-Only Support (FSLSSupp)
The application uses this bit to control the core's enumeration
speed. Using this bit, the application can make the core
enumerate as a FS host, even If the connected device supports
HS traffic. Do not make changes to this field after initial
programming.
 1'b0: HS/FS/LS, based on the maximum speed supported by
the connected device
 1'b1: FS/LS-only, even If the connected device can support
HS

FS/LS PHY Clock Select (FSLSPclkSel)
When the core is in FS Host mode
 2'b00: PHY clock is running at 30/60 MHz
 2'b01: PHY clock is running at 48 MHz
 Others: Reserved
When the core is in LS Host mode
 2'b00: PHY clock is running at 30/60 MHz. When the
UTMI+/ULPI PHY Low Power mode is not selected, use
30/60 MHz.
 2'b01: PHY clock is running at 48 MHz. When the UTMI+
PHY Low Power mode is selected, use 48MHz If the PHY
supplies a 48 MHz clock during LS mode.
 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
use 6 MHz when the UTMI+ PHY Low Power mode is
selected and the PHY supplies a 6 MHz clock during LS
mode. If you select a 6 MHz clock during LS mode, you must
do a soft reset.
 2'b11: Reserved
Notes:
 When Core in FS mode, the internal and external clocks have the same frequency.
 When Core in LS mode,
- If FSLSPclkSel = 2'b00: Internal and external clocks have the same frequency
- If FSLSPclkSel = 2'b10: Internal clock is the divided by eight version of external 48 MHz clock