reg_dramodt0

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF8010054`

Size: 32

Offset: 0x54

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`cfg_read_odt_chip` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`cfg_write_odt_chip` `RW 0x0`

reg_dramodt0 Fields

Bit	Name	Description	Access	Reset
31:16	`cfg_read_odt_chip`	iohmc_ctrl_mmr_top_inst.cfg_read_odt_chip[15:0] Name:Read ODT Control Description:ODT scheme setting for read command. Setting separated into 4 sections: [CS3][CS2][CS1][CS0] Each section consists of 4 bits to indicate which chip should ODT be asserted when write occurs on current CS. Eg: if we set to 16’b0000_0000_0010_0001, ODT will be asserted to chip0 and chip1 when write occurs to CS0 and CS1 respectively.	`RW`	`0x0`
15:0	`cfg_write_odt_chip`	iohmc_ctrl_mmr_top_inst.cfg_write_odt_chip[15:0] Name:Write ODT Control Description:ODT scheme setting for write command. Setting separated into 4 sections: [CS3][CS2][CS1][CS0] Each section consists of 4 bits to indicate which chip should ODT be asserted when write occurs on current CS. Eg: if we set to 16’b0000_0000_0010_0001, ODT will be asserted to chip0 and chip1 when write occurs to CS0 and CS1 respectively.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:16

cfg_read_odt_chip

iohmc_ctrl_mmr_top_inst.cfg_read_odt_chip[15:0]
Name:Read ODT Control
Description:ODT scheme setting for read command.
Setting separated into 4 sections: [CS3][CS2][CS1][CS0]
Each section consists of 4 bits to indicate which chip should ODT be asserted when write occurs on current CS.
Eg: if we set to 16’b0000_0000_0010_0001, ODT will be asserted to chip0 and chip1 when write occurs to CS0 and CS1 respectively.

RW

0x0

15:0

cfg_write_odt_chip

iohmc_ctrl_mmr_top_inst.cfg_write_odt_chip[15:0]
Name:Write ODT Control
Description:ODT scheme setting for write command.
Setting separated into 4 sections: [CS3][CS2][CS1][CS0]
Each section consists of 4 bits to indicate which chip should ODT be asserted when write occurs on current CS.
Eg: if we set to 16’b0000_0000_0010_0001, ODT will be asserted to chip0 and chip1 when write occurs to CS0 and CS1 respectively.

RW

0x0