enable

         Enable

Module Instance	Base Address	Register Address
`soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr`	`0xF8020100`	`0xF8020100`

Size: 32

Offset: 0x0

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`												`region3enable` `RW 0x0`	`region2enable` `RW 0x0`	`region1enable` `RW 0x0`	`region0enable` `RW 0x0`

enable Fields

Bit	Name	Description	Access	Reset
3	`region3enable`	Region 3 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled	`RW`	`0x0`
2	`region2enable`	Region 2 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled	`RW`	`0x0`
1	`region1enable`	Region 1 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled	`RW`	`0x0`
0	`region0enable`	Region 0 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled	`RW`	`0x0`