DIEPEMPMSK

         Device IN Endpoint FIFO Empty Interrupt Mask Register

Module Instance	Base Address	Register Address
`i_usbotg_0_DWC_otg_intreg`	`0xFFB00000`	`0xFFB00834`
`i_usbotg_1_DWC_otg_intreg`	`0xFFB40000`	`0xFFB40834`

Size: 32

Offset: 0x834

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESERVED` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`InEpTxfEmpMsk` `RW 0x0`

DIEPEMPMSK Fields

Bit

Name

Description

Access

Reset

31:16

RESERVED

RESERVED

RO

0x0

15:0

InEpTxfEmpMsk

IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk)
These bits acts as mask bits For DIEPINTn.
TxFEmp interrupt One bit per IN Endpoint:
Bit 0 For IN EP 0, bit 15 For IN EP 15

Value	Description
0x1	Mask IN EP0 Tx FIFO Empty Interrupt
0x2	Mask IN EP1 Tx FIFO Empty Interrupt
0x4	Mask IN EP2 Tx FIFO Empty Interrupt
0x8	Mask IN EP3 Tx FIFO Empty Interrupt
0x10	Mask IN EP4 Tx FIFO Empty Interrupt
0x20	Mask IN EP5 Tx FIFO Empty Interrupt
0x40	Mask IN EP6 Tx FIFO Empty Interrupt
0x80	Mask IN EP7 Tx FIFO Empty Interrupt
0x100	Mask IN EP8 Tx FIFO Empty Interrupt
0x200	Mask IN EP9 Tx FIFO Empty Interrupt
0x400	Mask IN EP10 Tx FIFO Empty Interrupt
0x800	Mask IN EP11 Tx FIFO Empty Interrupt
0x1000	Mask IN EP12 Tx FIFO Empty Interrupt
0x2000	Mask IN EP13 Tx FIFO Empty Interrupt
0x4000	Mask IN EP14 Tx FIFO Empty Interrupt
0x8000	Mask IN EP15 Tx FIFO Empty Interrupt

RW

0x0