DCTL

RESERVED

Enable Continue on BNA (EnContOnBNA)
This bit enables the DWC_otg core to continue on BNA for Bulk OUT endpoints. 
With this feature enabled, when a Bulk OUT endpoint receives a BNA interrupt
the core starts processing the descriptor that caused the BNA interrupt after 
the endpoint re-enables the endpoint. 
1'b0: After receiving BNA interrupt,the core disables the endpoint. When the 
      endpoint is re-enabled by the application,the core starts processing from 
      the DOEPDMA descriptor.  
1'b1: After receiving BNA interrupt, the core disables the endpoint. When the 
      endpoint is re-enabled by the application, the core starts processing from 
      the descriptor that received the BNA interrupt. This bit is valid only when
      OTG_EN_DESC_DMA == 1'b1. It is a one-time programmable after reset bit like 
      any other DCTL register bits.

NAK on Babble Error (NakOnBble)
Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for the
endpoint on which babble is received.

Ignore Frame number For Isochronous End points (IgnrFrmNum)
Do NOT program IgnrFrmNum bit to 1'b1 when the core is
operating in threshold mode.
Note:  When Scatter/Gather DMA mode is enabled this feature is not applicable to High Speed, High bandwidth transfers. When this bit is enabled, there must be only one packet per descriptor. 
 0: The core transmits the packets only in the frame number in which they are intended to be transmitted. 
 1: The core ignores the frame number, sending packets immediately as the packets are ready.
In Scatter/Gather DMA mode, if this bit is enabled, the packets are not flushed when a ISOC IN token is received for an elapsed frame.

When Scatter/Gather DMA mode is disabled, this field is used by the application to enable periodic transfer interrupt. The application can program periodic endpoint transfers for multiple (micro)frames.
 0: periodic transfer interrupt feature is disabled, application needs to program transfers for periodic endpoints every (micro)frame
 1: periodic transfer interrupt feature is enabled, application can program transfers for multiple (micro)frames for periodic endpoints.
In non Scatter/Gather DMA mode the application will receive transfer complete interrupt after transfers for multiple (micro)frames are completed.

Global Multi Count (GMC)
GMC must be programmed only once after initialization.
Applicable only For Scatter/Gather DMA mode. This indicates the
number of packets to be serviced For that end point before
moving to the next end point. It is only For non-periodic end
points.
 2'b00: Invalid.
 2'b01: 1 packet.
 2'b10: 2 packets.
 2'b11: 3 packets.
When Scatter/Gather DMA mode is disabled, this field is
reserved. and reads 2'b00.

Power-On Programming Done (PWROnPrgDone)
The application uses this bit to indicate that register
programming is completed after a wake-up from Power Down
mode.

Clear Global OUT NAK (CGOUTNak)
A write to this field clears the Global OUT NAK.

Set Global OUT NAK (SGOUTNak)
A write to this field sets the Global OUT NAK.
The application uses this bit to send a NAK handshake on all
OUT endpoints.
The application must set the this bit only after making sure that
the Global OUT NAK Effective bit in the Core Interrupt Register
(GINTSTS.GOUTNakEff) is cleared.

Clear Global Non-periodic IN NAK (CGNPInNak)
A write to this field clears the Global Non-periodic IN NAK.

Set Global Non-periodic IN NAK (SGNPInNak)
A write to this field sets the Global Non-periodic IN NAK.The
application uses this bit to send a NAK handshake on all nonperiodic
IN endpoints. The core can also Set this bit when a
timeout condition is detected on a non-periodic endpoint in
shared FIFO operation.
The application must Set this bit only after making sure that the
Global IN NAK Effective bit in the Core Interrupt Register
(GINTSTS.GINNakEff) is cleared

Test Control (TstCtl)
 3'b000: Test mode disabled
 3'b001: Test_J mode
 3'b010: Test_K mode
 3'b011: Test_SE0_NAK mode
 3'b100: Test_Packet mode
 3'b101: Test_Force_Enable
 Others: Reserved

Global OUT NAK Status (GOUTNakSts)
 1'b0: A handshake is sent based on the FIFO Status and the
NAK and STALL bit settings.
 1'b1: No data is written to the RxFIFO, irrespective of space
availability. Sends a NAK handshake on all packets, except
on SETUP transactions. All isochronous OUT packets are
dropped.

Global Non-periodic IN NAK Status (GNPINNakSts)
 1'b0: A handshake is sent out based on the data availability
in the transmit FIFO.
 1'b1: A NAK handshake is sent out on all non-periodic IN
endpoints, irrespective of the data availability in the transmit
FIFO.

Soft Disconnect (SftDiscon)
The application uses this bit to signal the DWC_otg core to do a
soft disconnect. As long as this bit is Set, the host does not see
that the device is connected, and the device does not receive
signals on the USB. The core stays in the disconnected state
until the application clears this bit.
The minimum duration For which the core must keep this bit Set
is specified in Table 5-46.
 1'b0: Normal operation. When this bit is cleared after a soft
disconnect, the core drives the phy_opmode_o signal on the
UTMI+ to 2'b00, which generates a device connect event to
the USB host. When the device is reconnected, the USB host
restarts device enumeration.
 1'b1: The core drives the phy_opmode_o signal on the
UTMI+ to 2'b01, which generates a device disconnect event
to the USB host.
Note: This bit can be also used for ULPI/FS Serial interfaces.
Note: This bit is not impacted by a soft reset.

Remote Wakeup Signaling (RmtWkUpSig)
When the application sets this bit, the core initiates remote
signaling to wake up the USB host. The application must Set this
bit to instruct the core to exit the Suspend state. As specified in
the USB 2.0 specification, the application must clear this bit 
1-15 ms after setting it.
Remote Wakeup Signaling (RmtWkUpSig) When LPM is enabled, 
In L1 state the behavior of this bit is as follows:
When the application sets this bit, the core initiates L1 remote signaling to
wake up the USB host. The application must set this bit to instruct the core
to exit the Sleep state. As specified in the LPM specification,
the hardware will automatically clear this bit after a time of 50 micro sec (TL1DevDrvResume)
after set by application. Application should not set this bit when GLPMCFG bRemoteWake
from the previous LPM transaction was zero.