FPGA_bridge_soc2fpga_1G_default Address Map

1 GB of FPGA slaves address space. This space is located in the FPGA core and accessed from the HPS through the HPS-FPGA AXI bridge. The L3 and MPU address regions provide windows of 4 GB into the FPGA slaves address space. The lower 1.5 GB of this space is mapped to two separate addresses. The lower 1.5 GB is accessible from 0x8000_0000 to 0xDFFF_FFFF and from 0x20_0000_0000 to 0x20_5FFF_FFFF in the HPS system memory map. This block represents the first 1G of space starting at 0x8000_0000.

Module Instance	Base Address	End Address
`i_fpga_bridge_soc2fpga_1G`	`0x80000000`	`0xBFFFFFFF`