SMMU_CB3_PMCFGR

         Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.

Note: For register and programming information, please refer to the ARM CoreLink MMU System Memory Management Unit Technical Reference Manual.

Module Instance	Base Address	Register Address
`i_aps_smmu_secure_registers`	`0xFA000000`	`0xFA023F00`

Size: 32

Offset: 0x23F00

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`NCG` `RO 0x0`								`Reserved`				`UEN` `RO 0x0`	`Reserved`		`EX` `RO 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`CCD` `RO 0x0`	`CC` `RO 0x0`	`SIZE` `RO 0x1F`						`N` `RO 0x3`