SFE

         Shadow FIFO Enable

Module Instance	Base Address	Register Address
`i_uart_uart_address_block`	`0xFF8D0000`	`0xFF8D0098`

Size: 32

Offset: 0x98

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_SFE_31to1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_SFE_31to1` `RO 0x0`															`sfe` `RW 0x0`

SFE Fields

Bit

Name

Description

Access

Reset

31:1

RSVD_SFE_31to1

Reserved bits [31:1] - Read Only

RO

0x0

sfe

Shadow FIFO Enable.
This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to
remove the burden of having to store the previously written value to the FCR in
memory and having to mask this value so that only the FIFO enable bit gets updated.
This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. If this
bit is set to zero (disabled) after being enabled then both the XMIT and RCVR
controller portion of FIFO's will be reset.

Value	Description
0x0	FIFOs are disabled
0x1	FIFOs are enabled

RW

0x0