SMMU_ITOP_GLBL
For integration test purposes, allows to enable or disable secure and nonsecure interrupts and write or read most significant bits of TCU MTLB and IPA RAMS.
Note: For register and programming information, please refer to the ARM CoreLink MMU System Memory Management Unit Technical Reference Manual.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_aps_smmu_secure_registers | 0xFA000000 | 0xFA002008 |
Size: 32
Offset: 0x2008
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
TCU_RAM_DATA RW 0x0 |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
GLBLSF1 RO 0x0 |
Reserved |
GLBLNSF1 RO 0x0 |
Reserved |
|||||||||||