IP_REV_ID2 

         <p>IP memory configuration</p>
Module Instance Base Address Register Address
ecc_nand_w_ecc_registerBlock 0xFFA20800 0xFFA20804

Size: 32

Offset: 0x4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

LUT_TBL_DEP

RO 0x8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RAM_TYPE

RO 0x2

ECC_SIZE

RO 0x4

DAT

RO 0x3

ADDR

RO 0x3

IP_REV_ID2 Fields

Bit Name Description Access Reset
19:16 LUT_TBL_DEP 
<p>Lookup Table Depth.</p>
<p><br />1 - 4 words (less than or equal) 64KB RAM size</p>
<p>2 - 8 words (less than or equal) 128KB RAM size</p>
<p>4 - 16 words (less than or equal) 256KB RAM size</p>
<p>8 - 20 words (less than or equal) 512KB RAM size</p>
<p>Others - UNUSED</p>
 RO 0x8
15:13 RAM_TYPE 
<p>Defines RAM type.</p>
<p>1 - single port</p>
<p>2 - simple dual port</p>
<p>3 - true dual port</p>
<p>Others - UNUSED</p>
 RO 0x2
12:10 ECC_SIZE 
<p>ECC Size.</p>
<p>Total number of ECC bits is dependent on the number of encoder/decoder implemented. This is specifying the width of the ECC syndrome.</p>
<p>1 - syndrome is 5 bits</p>
<p>2 - syndrome is 6 bits</p>
<p>3 - syndrome is 7 bits</p>
<p>4 - syndrome is 8 bits</p>
<p>Others - UNUSED</p>
 RO 0x4
9:5 DAT 
<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>
<p>0 - 8 bits</p>
<p>1 - 16 bits</p>
<p>2 - 32 bits</p>
<p>3 - 35 bits</p>
<p>4 - 64 bits</p>
<p>5 - 128 bits</p>
<p>6 - 256 bits</p>
<p>7 - 512 bits</p>
<p>Others - UNUSED</p>
 RO 0x3
4:0 ADDR 
<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>
<p>For example:</p>
<p>10 - 1Kbytes memory size 2^10 - 1K</p>
<p>15 - 32Kbytes memory size 2^15 - 32K</p>
 RO 0x3